1. Field of the Invention
The present invention relates to a decoder in a CD ROM driver and, more particularly, to a device for detecting an error from a digital data during decoding the digital data.
2. Discussion of the Related Art
In general, the CD ROM decoder has an error corrected in case the error is occurred in a data and determines final correction of the error in the data using an EDC (Error Detection Code).
FIG. 1 illustrates a data recording format on the CD ROM, in which the error detection code is shown.
Referring to FIG. 1, the error detection code is a 4 bytes parity calculated with the following equation for a total 2046 bytes including 12 bytes sync, 4 bytes header and 2048 bytes information data. ##EQU1##
That is, the CD ROM determines that there is an error in data if a remainder after making a dividing operation of the 2068 bytes including the sync, header, information data and error detection code with the above equation (1) is not "0". The process for decoding a signal recorded on a digital signal recording medium, such as the CD ROM includes a step for correcting errors, in which cases when a regular signal could not be read-in due to defects in the disc, mistakes in manufacturing, and errors in a servo or synchronizing signal are corrected. It also includes an error detection step, in which the error corrected data is once again inspected to confirm the state of the regular error correction.
A conventional device for detecting an error from within digital data in a CD ROM will be explained with reference to the attached drawings. FIG. 2 illustrates a block diagram showing the conventional device for detecting an error from a digital data in a CD ROM, and FIG. 3 illustrates a circuit diagram showing a detail of the dividing operation part shown in FIG. 2.
Referring to FIG. 2, the conventional device for detecting an error from within digital data in a CD ROM includes a data converting part 100 for converting a received byte unit parallel data into a bit unit series data in response to an operation clock signal, and an operation part 110 for subjecting the converted series data in bit unit series data to an operation according to the equation (1) in response to an operational clock signal, for producing final error(s).
Referring to FIG. 3, the operation part 110 includes a plurality of D-flipflops D1.about.D32 connected in series for temporarily storing the bit unit series data from the data converting part 100 in response to an operational clock signal for and producing the stored data after shifted, a first exclusive OR gate E1 for receiving and subjecting the bit unit series data from the data converting part 100 and an output from the flipflop D32 to an exclusive OR operation and for applying the exclusive OR operation result to the flipflop D1, a second exclusive OR gate E2 for receiving and subjecting the output from the flipflop D32 and an output from the flipflop D1 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D2, a third exclusive OR gate E3 for receiving and subjecting the output from the flipflop D32 and an output from the flipflop D3 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D4, a fourth exclusive OR gate E4 for receiving and subjecting the output from the flipflop D32 and an output from the flipflop D4 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D5, a fifth exclusive OR gate E5 for receiving and subjecting the output from the flipflop D32 and an output from the flipflop D15 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D16, a sixth exclusive OR gate E6 for receiving and subjecting the output from the flipflop D32 and an output from the flipflop D16 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D17, a seventh exclusive OR gate E7 for receiving and subjecting the output from the flipflop D32 and an output from the flipflop D31 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D32 again, and a NOR gate N1 for receiving each of the outputs from the flipflops D1.about.D32 and subjecting those outputs to an NOR operation.
The operation of the aforementioned system will be explained.
FIG. 4 illustrates a sequence of data reception for detecting an error. Byte unit parallel data stored in a memory (not shown), such as an SRAM or DRAM, i.e., the 2068 bytes including the sync, header, information data, error detection code shown in FIG. 1 are received at the data converting part 100. The received byte unit parallel data are converted into bit unit series data in response to a provided operation clock and applied to the operation part 110. The applied series data are 2068 bytes.times.8 bits=16544 bits of series data. An operation clock is required for each bit of the applied series data, i.e., 16544 operation clocks are required. In the application of data to the operation part 110, the 16544 bits of data are applied from the least significant bit (LSB) to the most significant bit (MSB) in an order as shown in FIG. 4.
The operation of the operation part 110 will be explained with reference to FIG. 3.
As explained, the operation part 110 has 32 flipflops D1.about.D32 connected in series, and, of the 32 flipflops D1.about.D32, one of the exclusive OR gates E1.about.E7 is connected to an input terminal of the first flipflop D1, the second flipflop D2, the fourth flipflop D4, the fifth flipflop D5, 16th flipflop D16, 17th flipflop D17 and 32nd flipflop D32. All the exclusive OR gates E1.about.E7 receive the output Q31 from the 32nd flipflop D32, and 16544 number of operation clocks are applied to each of the flipflops D1.about.D32. The NOR gate N1 receives each of the outputs Q0.about.Q31 from the flipflops D1.about.D32 and conducts an NOR operation to determine occurrence of error data finally. That is, when each of the data obtained in each of the flipflops D1.about.D32 according to the equation (1) is applied to the NOR gate N1, if all these applied data are "0", i.e., a low signal is produced, to determine that no error has occurred. And, of each of the data applied from each of the flipflops D1.about.D32 to the NOR gate N1, if a data of "1" is applied from any one of the data, a data of "1" is produced, to determine that an error has occurred and that the data correction has not been properly performed, finally.
The processing time for operations of digital data storage, error correction, error detection and data transmission in a conventional CD ROM drive will be examined with reference to FIG. 5. FIG. 5 illustrates time basis operations of the CD ROM decoder, wherein it can be seen that the CD ROM decoder processes one block data of 2352 bytes for the data storage, error correction, error detection and data transmission in time sharing.
In case of 1X CD ROM, the processing time for a process like that shown in FIG. 5 takes about 13.33 msec, and in case of 8X CD ROM, it takes 13.33 msec/8, i.e., about 1.67 msec. And, in case of 10X CD ROM, it takes 13.33 msec/10, i.e., about 1.333 msec. As can be know from this process, since reduction in the time required for the error detection allows allocation of more time to the data transmission and the like, a higher speed CD ROM drive could be realized.
Since the conventional device for detecting an error from within recorded digital data for the CD ROM driver converts bit unit parallel data stored in a memory into bit unit series data and applies an operation clock to every converted data bit, the lengthy error detection time causes a problem of hindering the CD ROM driver from being provided with a higher speed.